This invention relates generally to a flip-flop circuit for temporarily storing data in a logic device, and more particularly to an improved flip-flop circuit which prevents the occurrence of a soft error due to .alpha. rays and the like emitted from a trace amount of radioactive materials in a package material of a semiconductor.
FIG. 28 of the accompanying drawings illustrates an example of the logic construction of a flip-flop circuit. This circuit outputs the content of a data input 101 applied thereto through an input terminal In.sub.1 to an output signal terminal 104 when a clock signal 102 is at a logic "1" and also outputs the inversed content of the data input 101 to an inversed output terminal 103. When the clock signal 102 is at a logic "0", the circuit stores the content of the data input 101 at the time when the clock signal 102 is previously at the logic "1", and outputs the memory content to the output signal terminal 104 and the inversed memory content to the inversed output signal terminal 103. In the drawing, reference numeral 109A represents an inverter, 106A to 106C are OR gates, 107 is an AND gate and 105 in a feedback signal line.
FIG. 29 is a conventional circuit diagram to accomplish the flip-flop circuit shown in FIG. 28. This circuit uses an emitter coupled logic (hereinafter referred to as "ECL") as a basic gate, and each gate is constituted so as to correspond to each of the constant current generators 1118, 1128 and 1138. Let's consider the gate corresponding to the constant current generator 1118. The input terminal of this gate is the base of each of the transistors 1111 and 1112, and its NOR output and OR output can be obtained from the common collector of the transistors 1111, 1112 and the collector of the transistor 1113. This also holds true of the other gates.
Next, the operation in FIG. 29 which corresponds to the AND gate 107 of FIG. 28 will be described. In the circuit shown in FIG. 29, the OR output of each of the three gates is obtained from the collector of the transistor 1113, 1123, 1133 as described above, and these three collectors in this circuit are wired (1103) in common and are outputted to 104 through an emitter follower transistor 1101. This wiring 1103 can logically provide AND from the OR outputs of the three gates. On the other hand, the NOR output of each gate is outputted through the emitter follower transistor 1114, 1124, 1134, and the emitters of these three transistors are wired (1104) in common. Therefore, the NOR outputs of these three gates can logically provide OR. According to the De Morgan's rules, this is equivalent to the negation of AND of the OR output, so that the circuit construction shown in FIG. 29 can provide the output signal 104 and the inversed output signal 103 in the same way as the circuit shown in FIG. 28. For the detail of the circuits shown in FIGS. 28 and 29, refer to the specification of Japanese Patent Laid-Open Patent No. 198921/1983.
It has been clarified recently that .alpha. rays emitted from a trace amount of radioactive materials in a package material of a semiconductor causes a soft error of memories and flip-flop circuits. FIG. 30 shows the case where the .alpha. ray is incident to a bipolar transistor as an example of a semiconductor chip. Reference numerals 126, 127 and 129 represent emitter, base and collector regions, respectively, and reference numeral 130 does a depletion layer of a PN junction formed by the collector 129 and a substrate 131. When the .alpha. ray is incident, electron-hole pairs are generated along the orbit 120 of the .alpha. ray. Among these electron-hole pairs generated in these regions, it is the electron-hole pair developing in the depletion layer 130 and the substrate 131 that exerts the greatest influences.
Let's consider the electrons. The electrons generated in the depletion layer 130 are attracted to the collector by the electric field of the PN junction. The electrons generated in the substrate 131 reach the depletion layer 130 due to diffusion and are likewise attracted to the collector. Therefore, the influence of the incident .alpha. ray appears as noise on current, and this current flows from the collector of the transistor, to which the .alpha. ray is incident, to the substrate.
Though the description given above deals with the bipolar transistor, the situation is the same with memory or logic LSIs. The report on the soft error of bipolar memories is described, for example, in "Transactions of the Institute of Electronics and Communication Engineers", Vol. 63-C, No. 2 (1980-2), (Mitsusada et al; "Soft Error of High Speed Bipolar RAM due to .alpha. particles"). On the other hand, no report has yet been made on the occurrence of the soft error in logic LSIs. This is because a circuit current is greater in the logic LSI than in the memory LSI and the signal amplitude is also greater. However, since it is expected that the miniaturization of devices will further proceed and their performance will become higher and higher in future with a decreasing parasitic capacity, the amount of stored charge will also decrease and the soft error will become a problem in the logic LSI, too.
As the problem inherent to the logic LSI, the following problem can be pointed out. Since the number of signal pins is great in the logic LSI, a chip bonding method which is referred to as CCB ("Controlled Collapse Bonding") has been used in place of conventional wire bonding (for example, "IEEE Journal of Solid State Circuits", Vol. SC-14, No. 5, pp. 818-822 (1979-11)). According to this method, solder balls are placed on the entire surface of the chip, but the radioactive isotopes (e.g. Ra, Am) contained as impurities in the solder will result in the soft error of the logic LSI. Since the solder ball is bonded to the chip, it becomes impossible to cut off the .alpha. ray by covering the chip by any material, for instance, and hence those circuits which are highly resistant to the .alpha. rays will become necessary.